Expert / Senior Logic Design Engineer (FPGA, ASIC)

About the Project

We are looking for a Logic Design Engineers to join a team developing next-generation FPGA and ASIC-based control and measurement platforms for quantum computing systems.

We're looking for engineers with an R&D mindset to join a dedicated team integrated into the client’s company. We're looking for two levels - Senior and Expert:

• Senior: 4+ years of relevant professional experience
• Expert: Significantly deeper experience with demonstrated ownership of architecture and complex digital subsystems

The client is building advanced hardware and software solutions that enable precise, real-time control of complex quantum systems - from individual qubits to large-scale architectures. The work involves designing high-performance digital logic with extremely demanding requirements for latency, timing determinism, and reliability.

The engineering organization consists of a logic design team, a verification team, and a model team that builds high-level C and C++ models to compare against FPGA logic implementations for verification.

Potential project options could include working on a standalone FPGA-based project or contributing to the new ASIC development.

You will work in close collaboration with system architects, verification engineers, software developers, and hardware specialists in an international engineering environment.

Remote work is fully supported.

Responsibilities:

• Design, implement, and optimize complex, configurable, ultra-low-latency digital logic using SystemVerilog
• Develop RTL for high-performance FPGA and ASIC applications, including signal processing pipelines, waveform generation, and deterministic real-time control
• Participate in (or lead) the full digital design lifecycle: architecture/microarchitecture definition, RTL implementation, integration, synthesis, and timing closure
• Optimize designs for timing performance, latency, resource utilization, scalability, and power efficiency
• Address complex timing challenges, including critical path optimization, clock-domain crossing (CDC), and synchronization
• Define and implement hardware-software interfaces
• Collaborate closely with verification engineers to ensure functional correctness and robust coverage
• Contribute to design reviews, technical decision-making, and continuous improvement of engineering practices
• (Expert level) Drive end-to-end digital IP development and make architectural trade-off decisions

Must-have

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field (or equivalent practical experience)
• Strong professional experience in FPGA and/or ASIC digital logic design
• Solid hands-on expertise in SystemVerilog and RTL design
• Proven experience with timing analysis, timing closure, synthesis, and performance optimization
• Experience designing low-latency / deterministic digital systems
• Understanding of high-speed interfaces (AXI, PCIe, DDR, or similar)
• Ability to work effectively in an international team and communicate technical topics clearly in English

Nice-to-have:

• Experience with ultra-low-latency or nanosecond-scale timing systems
• Background in signal processing (DSP), waveform generation, or high-speed data acquisition
• Experience with ASIC-oriented RTL development and reusable digital IP
• Knowledge of Python, Tcl, or other scripting languages for EDA automation
• Previous work in quantum computing, high-performance instrumentation, telecommunications, semiconductor, or similar domains
• Experience leading technical design reviews or mentoring other engineers (especially for Expert level)
• Familiarity with hardware-software co-design

Tech Stack

• Primary HDL: SystemVerilog
• Design targets: FPGA and ASIC
• Key focus areas: RTL design, timing closure, low-latency architectures, CDC
• Interfaces: AXI, PCIe, DDR, proprietary high-speed interconnects
• Domains: Real-time control, signal processing, waveform generation
• Automation: Python / Tcl (preferred)
• Additional tools: Industry-standard synthesis, place & route, and static timing analysis tools

Possible Contract Types:

• Bulgaria-employment contract
• Slovakia-employment contract
• Czech Republic- employment contract
• Poland-B2B
• Romania-B2B
• Spain-employment contract
• Ukraine - B2B (FOP3 contract)

Interview Process:

• HR Interview
• 1-2 interviews on the Client's side.