Expert / Senior Logic Design Engineer (FPGA, ASIC)

About the Company

The client is a technology company that develops advanced control and measurement systems for quantum computers. Their platforms sit between classical computing and quantum processors, enabling researchers and engineers to precisely control, measure, and orchestrate qubits in real time.

The company builds high-performance hardware and software solutions used for:

• Real-time quantum control and readout
• Ultra-low-latency feedback and feed-forward
• High-speed waveform generation and signal processing
• Scalable control of quantum processors (from single qubits to large multi-qubit systems)
• Automated calibration and hybrid quantum-classical workflows

Their product portfolio includes modular high-density quantum control platforms, ultra-fast quantum controllers, high-precision multi-channel DACs, and supporting software for pulse-level programming and automated calibration. These systems are designed to deliver deterministic timing, nanosecond-scale responsiveness, and the reliability required for advanced quantum experiments and scalable quantum computing.

The engineering organization consists of specialized teams working on logic design, verification, and high-level modeling (including C/C++ reference models). Engineers collaborate closely with system architects, software developers, and quantum physicists in an international R&D environment.

About the Project

We are looking for Logic Design Engineers to join a team developing next-generation FPGA and ASIC-based control and measurement platforms for quantum computing systems.

We’re looking for engineers with an R&D mindset to join a dedicated team integrated into the client’s company. Two levels are open:

• Senior: 4+ years of relevant professional experience
• Expert: Significantly deeper experience with demonstrated ownership of architecture and complex digital subsystems

The work involves designing high-performance digital logic with extremely demanding requirements for latency, timing determinism, and reliability. Potential project options include working on standalone FPGA-based projects or contributing to new ASIC development.

You will collaborate closely with system architects, verification engineers, software developers, and hardware specialists in an international engineering environment. Remote work is fully supported.

Responsibilities

• Design, implement, and optimize complex, configurable, ultra-low-latency digital logic using SystemVerilog
• Develop RTL for high-performance FPGA and ASIC applications, including signal processing pipelines, waveform generation, and deterministic real-time control
• Participate in (or lead) the full digital design lifecycle: architecture/microarchitecture definition, RTL implementation, integration, synthesis, and timing closure
• Optimize designs for timing performance, latency, resource utilization, scalability, and power efficiency
• Address complex timing challenges, including critical path optimization, clock-domain crossing (CDC), and synchronization
• Define and implement hardware-software interfaces
• Collaborate closely with verification engineers to ensure functional correctness and robust coverage
• Contribute to design reviews, technical decision-making, and continuous improvement of engineering practices
• (Expert level) Drive end-to-end digital IP development and make architectural trade-off decisions

Must-have

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field (or equivalent practical experience)
• Strong professional experience in FPGA and/or ASIC digital logic design
• Solid hands-on expertise in SystemVerilog and RTL design
• Proven experience with timing analysis, timing closure, synthesis, and performance optimization
• Experience designing low-latency, deterministic, or real-time digital systems
• Understanding of high-speed interfaces (AXI, PCIe, DDR, JESD, high-speed ADC/DAC, or similar)
• Ability to work effectively in an international team and communicate technical topics clearly in English

Nice-to-have

• Experience with ultra-low-latency or nanosecond-scale timing systems
• Background in signal processing (DSP), waveform generation, pulse sequencing, or high-speed data acquisition
• Experience with real-time feedback, closed-loop, or feed-forward control systems
• Experience with ASIC-oriented RTL development and reusable digital IP
• Knowledge of Python, Tcl, or other scripting languages for EDA automation
• Previous work in quantum computing, high-performance instrumentation, telecommunications, semiconductor, or similar domains
• Experience leading technical design reviews or mentoring other engineers (especially for Expert level)
• Familiarity with hardware-software co-design
• Experience with Vivado / Versal or similar FPGA toolchains

Tech Stack

• Primary HDL: SystemVerilog
• Design targets: FPGA and ASIC
• Key focus areas: RTL design, timing closure, low-latency architectures, CDC
• Interfaces: AXI, PCIe, DDR, high-speed ADC/DAC, proprietary interconnects
• Domains: Real-time control, signal processing, waveform generation
• Automation: Python / Tcl (preferred)
• Additional tools: Industry-standard synthesis, place & route, and static timing analysis tools

Possible Contract Types

• Bulgaria – employment contract
• Slovakia – employment contract
• Czech Republic – employment contract
• Poland – B2B
• Romania – B2B
• Spain – employment contract
• Ukraine – B2B (FOP 3 group)

Interview Process

• HR Interview
• 1–2 interviews on the Client’s side