Shevach, Image and Video Processing Practitioner, Computer Vision, AI & ML

AI and Machine Learning, Video Game (5.0 yr.), Embedded Firmware

Summary

* 25 years in Israel high-tech (Video, Streaming) , 5 years with Cloud Gaming (Electronic Arts)
* Scalable Video Streaming among LEO satellites (research project of Ben Gurion University)
* Cloud Gaming: encoding, decoding, low latency streaming (e.g. RTP/SRT), error resilience etc.
* Video Codecs: Subcontracting with Visionular on improving coding efficiency of its own HEVC
encoder.
* Subcontracting with DSP-IP - military projects
* Video optimization and hevc codec development (Beamr Imaging)
* Python Programming: development automated testing systems (CI), proofs of concept, computer vision with packages cv2 and cvlib.
* Artificial Intelligence: genetics/evolutionary optimization of video codec parameters, facial expressions detection with CNN.
* 360/VR: subcontracting with Texel (texel.live) - tiled streaming Computer Vision: OpenCV (including python cv2).
* NVIDIA/AMD products: evaluation and modification hw encoders: Tesla T4, A40) of NVIDIA and Navi21 of AMD.
* and several technical papers and several technical papers

Selected Experience:

Cloud Gaming: encoding, decoding, low latency streaming (e.g. RTP/SRT), error concealment etc.
Video Codecs:
- subcontracting with Visionular on improving HEVC codec
- subcontracting with DSP-IP - military projects
- video optimization and hevc codec development (Beamr Imaging)
Python Programming: development automated testing systems (CI), proofs of concept, computer vision with packages cv2 and cvlib.
Artificial Intelligence: genetics/evolutionary optimization of video codec parameters, facial expressions detection with CNN.
360/VR: subcontracting with Texel (texel.live) Computer Vision: OpenCV (including python cv2),
NVIDIA/AMD products: evaluation and modification hw encoders: Tesla T4, A40) of NVIDIA and Navi21 of AMD

Work Experience

SW Engineer, Encoding and Decoding

Duration: August 2018 - May 2023

Cloud Gaming: incorporation of HEVC, Low latency video players for MAC OS, Enhancement of Error handling on client side

Responsibilities: Subcontracting with Visionular on improving HEVC codec subcontracting with DSP-IP - military projects video optimization and HEVC codec development (Beamr Imaging)

Technologies: HEVC, RTP/SR T, error concealment

SW Engineer, Metadata Preservation

Duration: March 2014 - May 2018

Responsibilities: Preservation of mp4-metadata during re-compression BluRay authoring Closed Caption HEVC/A VC encoding on cloud Face Detection HDR to SDR (Tone Mapping)

Technologies: HEVC, mp4-metadata, BluRay, Face Detection, HDR to SDR

SW Engineer, AVC/H.264 Encoder

Duration: 2008-2013 (Dec.)

Responsibilities: Implementation of AVC/H.264 encoder on digital cameras Participation in design of HEVC/H.265 codec Implementation and design of Error Handling for H264, MPEG4, AVS. Implementation of intra prediction, transforms on parallel SIMDs. SW implementation of fast forward/backward playback mode Participation in architecture design of multi-standard video decoder for STBs

Technologies: AVC/H.264, HEVC/H.265, H264, MPEG4, AVS, SIMDs, STBs

SW Engineer, Firmware Engineering, Broadcom Israel

Duration: 2003-2008

Responsibilities: Real-time Firmware engineering, chip architecture design, HW verification and algorithm developing. Implementation new features for MPEG2/MPEG-4/A VC encoder: T-STD and P-STD compliancy, VBV compliancy, DVD compliancy, 3:2 cadence detection, scene change detection, white-noise detection. Bit-exact C models of HW units for verification purpose, e.g. CABAC. Design of spatial-temporal motion compensation video preprocessor. Participation in MPEG2-H264 transcoder architecture design Participation in H.264 encoder architecture design Participation in HW optimization, e.g. HW sharing

Technologies: MPEG2, MPEG-4, AVC, T-STD, P-STD, VBV, DVD, CABAC, motion compensation

SW Engineer, Video-Audio Compression, Mango DSP, Jerusalem

Duration: 2000-2003

Responsibilities: Embedded programming and algorithm developing: Implementation of different video-audio compression standards on TMS320C67x/62x/64x (TI), e.g. H263, MPEG4, JPEG. Developing, implementation and optimization of different image/audio processing algorithms on parallel DSPs.

Technologies: TMS320C67x/62x/64x, H263, MPEG4, JPEG, DSPs

Education

B.A. of Mathematics & Computer Sc., 1992-1995
M.A. with Thesis Work on Mathematics & Computer Science department. Total grade 93 (advisor prof. J.Arazy), graduated with Honor, 1998-2000
Starting PhD in Technion, Applied Mathematics (not finished), 2003

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