Markus Leiter FPGA Engineer

Embedded Firmware (5.0 yr.), Embedded Software (5.0 yr.)

Summary

Embedded Firmware (5.0 yr.), Embedded Software (5.0 yr.)

C1 (Advanced) English

Senior (5-10 years)

Austria (Hagenberg im Muehlkreis) , (UTC+01:00)

Field-Programmable Gate Array (FPGA) 5.0 yr.

Embedded Systems

verification testing

system architecture 4.0 yr.

Efinix Intel Quartus Lattice Diamond Lattice ICE40 Lattice Radiant SoC FPGA Xilinx Vivado

ID: 100-253-119

Last Updated: 2024-09-11

Last Actualized: 21 Dec 2024